-60-Second Timer-
-design criteria-
Design a digital Sixty Second Timer that counts from 00 to 60.
- This design has two control inputs and two output displays.
- The two inputs are Clock and Reset. The Clock signal is a 1 Hz square wave that controls the count rate.
- The Reset signal, when it is a logic zero, resets and holds the count at zero.
- When the Reset signal is a logic one, counting is enabled. When the count reaches sixty seconds, the counting resets at zero.
-design constraints-
- The two output displays are common cathode seven-segment displays that will require a multiplexed signal.
- Each display will use a 74LS48 BCD-To-Seven-Segment display driver in Design Mode. (DEC_BCD_7 in PLD Mode)
- The ones-unit display (0-9) is controlled by a synchronous counter designed with a 74LS163 MSI counter IC. (CNTR_4BIN_S in PLD Mode)
- The tens-unit display (0-6) is controlled by an asynchronous counter designed with SSI logic gates (J/K).
- Any additional logic may be used as needed to support the counter designs.
-procedure-
Much like the Now Serving project, I began this circuit by building the counter for the ones digit, as seen from the green wiring. This was a simple MSI counter as seen in the above picture. The clock signal was sent into the counter, with a loaded number of 0000, as seen in inputs A, B, C, and D.
From there, the output signal was truncated to reset when the binary count 1001 was seen by the 4-Input NAND gate. With the use of inverters, a logic zero is sent to the load input of the counter. In turn, this portion circuit counts continuously from 0-9, unless clear is pressed.
Clear was hooked up through PIO41, which was BTN0 (button zero). When button zero was pressed, an active high would be sent through an inverter to activate the clear portion of the counter.
From there, the output signal was truncated to reset when the binary count 1001 was seen by the 4-Input NAND gate. With the use of inverters, a logic zero is sent to the load input of the counter. In turn, this portion circuit counts continuously from 0-9, unless clear is pressed.
Clear was hooked up through PIO41, which was BTN0 (button zero). When button zero was pressed, an active high would be sent through an inverter to activate the clear portion of the counter.
After completing the ones section, I moved on the to asynchronous SSI counter for the 10's digit. Since this was a sixty second timer, we needed the count to range from 0-6. I accomplished this by adding a 4-input NOR gate to the ones circuit to recognize the number 0000. This way, each time the ones counted to ten, the tens digit would cycle to the next count. This can be seen in the green wiring at the bottom of the image.
From there, the counter simply needed to reset when the number seven was seen. Looking at the green wiring at the top of the image, you can see this. In hindsight, 3-inpur NAND gates could have been used in place of the 4-inputs since the 4th bit (D) is never used.
From there, the counter simply needed to reset when the number seven was seen. Looking at the green wiring at the top of the image, you can see this. In hindsight, 3-inpur NAND gates could have been used in place of the 4-inputs since the 4th bit (D) is never used.
Now that the ones and tens digits were counting the appropriate numbers, it was time to fine tune the circuit. Without these additions, the sixty second timer would actually count 0-59. The approach I took to solving this problem was to build another reset circuit that would reset the entire counter when the number 61 was seen. I chose the number 61 because resetting at the number 60 would actually cause the circuit to count from 0-59.
The design of the circuit was to add another 4-input NAND gate to the tens gate to recognize the number 6, with a separate 4-input NAND gate to recognize the number 1. When both of these gates saw their assigned numbers, a logic zero was sent to an or gate, which in turn, reset the 10s digit to zero; thus beginning the count at 00 again.
The design of the circuit was to add another 4-input NAND gate to the tens gate to recognize the number 6, with a separate 4-input NAND gate to recognize the number 1. When both of these gates saw their assigned numbers, a logic zero was sent to an or gate, which in turn, reset the 10s digit to zero; thus beginning the count at 00 again.
The complete sixty second timer circuit can be seen here. In simulation, it functions properly, and counts from 00-60. From here the design was exported and tested on the DMS board to verify functionality.
-errors-
The design worked flawlessly in simulation, but exporting the design to the DMS wasn't the smoothest operation. After exporting the circuit, it would appear to work properly for the first cycle, but when the counter reached 60, it would reset to 40 instead of 00.
Much time was spent troubleshooting the issue and trying new designs. In an effort to verify that the seven segment display was seeing the same binary count that I was seeing in the simulation, I added LED outputs LD0-3, and PIO37-40. I expected to see the tens digit counting properly, with the seven segment display counting improperly. To my surprise, adding the LEDs between the counter and decoder actually fixed the problems I experienced during on the DMS board.
This didn't make any sense to me logically, but the presumption is that the LEDs are actually working like pull-down resistors to the tens counter.
Much time was spent troubleshooting the issue and trying new designs. In an effort to verify that the seven segment display was seeing the same binary count that I was seeing in the simulation, I added LED outputs LD0-3, and PIO37-40. I expected to see the tens digit counting properly, with the seven segment display counting improperly. To my surprise, adding the LEDs between the counter and decoder actually fixed the problems I experienced during on the DMS board.
This didn't make any sense to me logically, but the presumption is that the LEDs are actually working like pull-down resistors to the tens counter.