-DESIGN CRITERIA-
In this project, we needed to design a "Now Serving" sign that displayed a count from 00 to 80. The count would begin at 00 and advance by one digit each time a button was pressed. Also, a button was added to clear the count back down to 00.
-design Constraints-
- The two output displays are common cathode seven-segment displays.
- The two displays require a multiplexed design.
- The ones-unit display (Least Significant Digit) is controlled by an asynchronouscounter designed with a 74LS93 MSI counter IC. The PLD Mode equivalent of the74LS93 is the CNTR_4BIN_AS. (Counter_4-Bit_Binary_Asynchronous)
- The tens-unit display (Most Significant Digit) is controlled by an asynchronous counterdesigned with SSI logic gates (D or J/K).
- Any additional logic may be used as needed to support the counter designs.
- Add a design feature that holds the count when it reaches 80.
-procedure-
The multiplexer used for the Now Serving sign was given to us for this assignment, and thank goodness for that!
What happens in this multiplexer is that both seven segment displays are never on at the same time. As we learned earlier in the year, most digital signage is not constantly on because it helps in energy efficiency. In this case, the two digits I used are being turned on and off alternatively at 2KHz. It is impossible to see the LEDs turning on and off that many times in one second, so they appear on at all times.
Although this portion of the schematic was given to us, we still needed to build the input side of the seven segment displays, so they would know what numbers to display.
What happens in this multiplexer is that both seven segment displays are never on at the same time. As we learned earlier in the year, most digital signage is not constantly on because it helps in energy efficiency. In this case, the two digits I used are being turned on and off alternatively at 2KHz. It is impossible to see the LEDs turning on and off that many times in one second, so they appear on at all times.
Although this portion of the schematic was given to us, we still needed to build the input side of the seven segment displays, so they would know what numbers to display.
To begin the design, I built an MSI circuit that would control the ones digit. Since this counter is designed to count to 15, the outputs needed to be truncated to reset the count to zero when the counter reached 10 (1010). As you can see to the right, the w, x, y, and z LEDs were used to verify the count was reaching 1010. From there, a 4-input AND gate was fed logic 1s, using inverters where necessary. The output of that AND gate was used for two purposes: 1) to reset the count to zero, and 2) to trigger the clock of the tens digit......
This circuit is was used to count the tens digit. The wire triggering the clock is coming from the OR gate in the previous picture. When the AND gate sends a logic 1 out to the OR gate, the OR gate then sends a logic 1 to the positive-edge triggered D flip flops.
From here, the same logic happens as was in the MSI circuit, however, SSI logic was used as it was a design constraint.
Since the count had to go 00-80, the tens digit only needed to count to the number 8. As you can see, this design was also truncated to send a logic 0 out when the NAND gate "saw" the number 8 as all ones. The output from the NAND gate was then sent to interrupt the original clock.....
From here, the same logic happens as was in the MSI circuit, however, SSI logic was used as it was a design constraint.
Since the count had to go 00-80, the tens digit only needed to count to the number 8. As you can see, this design was also truncated to send a logic 0 out when the NAND gate "saw" the number 8 as all ones. The output from the NAND gate was then sent to interrupt the original clock.....
As you can see in the complete circuit, when the tens digit recognized and 8, a logic zero would be sent to a 2-input AND gate on the ones-clock. This in turn would cause the counter to pause and hold at the number 80 until Reset (PIO44/BTN0) was pressed.
Although there are many variations to make this Now Serving Circuit, this was the most logical approach for me. Once the circuit simulated properly, the PLD was exported to the DMS.
Although there are many variations to make this Now Serving Circuit, this was the most logical approach for me. Once the circuit simulated properly, the PLD was exported to the DMS.
-errors-
During the PLD process, I did not experience any wiring errors, but I did experience an error in the tens digit. My circuit would count from 00-80, but when reset was pressed, it would reset to 10, not 00. After multiple attempts at troubleshooting, it was determined that the MSI counter used for the tens digit was negative edge triggered. What was happening was that the circuit was being cleared to a zero, but when the button was released, the clock signal would drop from high to low. This low drop caused the MSI counter on the tens digit to clock to the next binary count, 0001. This problem was solved by inverting the clock signal on the MSI counter; however, this was not the appropriate way to build the circuit. It was correct and worked properly, but the design constraints stated to build the tens digit with an SSI counter, not an MSI.
After realizing this, the tens digit portion of the circuit was rebuilt. Since the SSI counter is positive-edge triggered, it did not need to be inverted like the MSI I had initially built. Trying to figure out what was wrong with my initial MSI circuit was a bit of a headache because of the negative-edge trigger. The circuit is much easier to build and understand using an SSI counter, and I believe that is the reason SSI was chosen over MSI for the tens digit.
Also, while testing the circuit on the DMS, the next button would randomly skip numbers. This was do to a "bounce" effect seen in the push button switch. The signal is bouncing causing the DMS to think you pushed the button more than one time. This is not a problem with my circuit design, but with the DMS buttons itself.
After realizing this, the tens digit portion of the circuit was rebuilt. Since the SSI counter is positive-edge triggered, it did not need to be inverted like the MSI I had initially built. Trying to figure out what was wrong with my initial MSI circuit was a bit of a headache because of the negative-edge trigger. The circuit is much easier to build and understand using an SSI counter, and I believe that is the reason SSI was chosen over MSI for the tens digit.
Also, while testing the circuit on the DMS, the next button would randomly skip numbers. This was do to a "bounce" effect seen in the push button switch. The signal is bouncing causing the DMS to think you pushed the button more than one time. This is not a problem with my circuit design, but with the DMS buttons itself.